9.1.3 Interfacing
The input–output interface connects
the computer to the outside world, and is therefore an essential part of the
computer system. When the CPU puts the address of a peripheral onto the address
bus, the input–output interface decodes the address and identifies the unique
computer peripheral with which a data transfer operation is to be executed. The
interface also has to interpret the command on the control bus so that the
timing of the data transfer is correct. One further very important function of
the input–output interface is to provide a physical electronic highway for the
flow of data between the computer data bus and the external peripheral. In many
computer applications, including their use within intelligent devices, the
external peripheral requires signals to be in analogue form. Therefore the
input–output interface must provide for conversion between these analogue
signals and the digital signals required by a digital computer. This is
satisfied by analogue-to-digital and digital-to-analogue conversion elements
within the input–output interface.
A standard form of interface used to
connect a computer to its peripheral devices is the UART (Universal
Asynchronous Receiver/Transmitter). This has been used for around 30 years. A
newer interface protocol that is particularly suitable for connecting a large
number of devices and providing for communication between different computers
is the PCI (Peripheral Component Interconnect) interface. Very recently, an
alternative protocol called the Universal Serial Bus (USB) has been developed
that is rapidly gaining in popularity.
The rest of this section presents
some elementary concepts of interfacing in simple terms. A more detailed
discussion follows later in Chapter 10, where the combination of intelligent
devices into larger networks is discussed.
Address decoding
A typical address bus in a
microcomputer is 16 bits wideĊ, allowing 65 536 separate addresses to be
accessed in the range 0000–FFFF (in hexadecimal representation). Special
commands on some computers are reserved for accessing the bottom end 256 of
these addresses in the range 0000–00FF, and, if these commands are used, only 8
bits are needed to specify the required address. For the purpose of explaining
addressdecoding techniques, the scheme below shows how the lower 8 bits of the
16-bit address line are decoded to identify the unique address referenced by
one of these special commands. Decoding of all 16 address lines follows a
similar procedure but requires a substantially greater number of integrated
circuit chips.
Address decoding is performed by a
suitable combination of logic gates. Figure 9.4 shows a very simple hardware
scheme for decoding 8 address lines. This consists
of 256 8-input NAND gates, which each
uniquely decode one of 256 addresses. A NAND gate is a logic element that only
gives a logic level 1 output when all inputs are zero, and gives a logic level
0 output for any other combination of inputs. The inputs to the NAND gates are
connected onto the lower 8 lines of the address bus and the computer
peripherals are connected to the output of the particular gates that decode
their unique addresses. There are two pins for each input to the NAND gates
that respectively invert and do not invert the input signal. By connecting the
8 address lines appropriately to these two alternative pins at each input, the
gate is made to decode a unique address. Consider for instance the pin
connections shown in Figure 9.5. This NAND gate decodes address C5
(hexadecimal), which is 11000101 in binary. Because of the way in which the
input pins to the chip are connected, the NAND gate will see all zeros at its
input when 11000101 is on the lower 8 bits of the address bus and therefore
will have an output of 1. Any other binary number on the address bus will cause
this NAND gate to have a zero output.
Data transfer control
The transfer of data between the
computer and peripherals is managed by control and status signals carried on
the control bus that determine the exact sequencing and timing of I/O
operations. Such management is necessary because of the different operating
speeds of the computer and its
peripherals and because of the multi-tasking operation of many computers. This
means that, at any particular instant when a data transfer operation is
requested, either the computer or the peripheral may not be ready to take part
in the transfer. Typical control and status lines, and their meanings when set
at a logic level of 1, are shown below.
BUSY Peripheral device busy
READY Peripheral device ready for
data transfer
ENABLE CPU ready for data transfer
ERROR Malfunction on peripheral
device
Similar control signals are set up by
both the computer and peripherals, but different conventions are often used to
define the status of each device. Differing conventions occur particularly when
the computer and peripherals come from different manufacturers, and might mean
for instance that the computer interprets a logic level of 1 as defining a
device to be busy but the peripheral device uses logic level 0 to define
‘device busy’ on the appropriate control line. Therefore, translation of the
control lines between the computer and peripherals is required, which is
achieved by a further series of logic gates within the I/O interface.
9.1.4 Practical considerations in
adding computers to measurement systems
The foregoing discussion has
presented some of the necessary elements in an input–output interface in a
relatively simplistic manner that is just sufficient to give the reader the
flavour of what is involved in an interface. Much fine detail has been omitted,
and the amount of work involved in the practical design of a real interface
should not be underestimated. One significant omission so far is discussion of
the scaling that is generally required within the analogue–digital interface of
a computer. The raw analogue input and output signals are generally either too
large or too small for compatibility with the operating voltage levels of a
digital computer and they have to be scaled upwards or downwards. This is
normally achieved by operational amplifiers and/or potentiometers. The main
features of an operational amplifier are its high gain (typically × 1 000 000)
and its large bandwidth (typically 1 MHz or better). However, when one is used
at very high frequencies, the bandwidth becomes significant. The quality of an
amplifier is often measured by a criterion called the gain–bandwidth product,
which is the product of its gain and bandwidth. Other important attributes of
the operational amplifier, particularly when used in a computer input–output
interface or within intelligent devices, are its distortion level, overload
recovery capacity and offset level. Special instrumentation amplifiers that are
particularly good in these attributes have been developed for instrumentation
applications, as described in section 5.5.1.
Suitable care must always be taken
when introducing a computer into a measurement system to avoid creating sources
of measurement noise. This applies particularly where one computer is used to
process the output of several transducers and is connected to them by signal
wires. In such circumstances, the connections and connecting wires can create
noise through electrochemical potentials, thermoelectric potentials, offset
voltages introduced by common mode impedances, and a.c. noise at power, audio
and radio frequencies. Recognition of all these possible noise sources allows
them to be eliminated in most cases by employing good practice when designing
and constructing the measurement system.
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